An Efficient Aopproach to Constrained Via Minimization for Two-Layer VLSI Routing
نویسندگان
چکیده
| Constrained Via Minimization is the problem of reassigning wire segments of a VLSI routing so that the number of vias is minimized. In this paper, a new approach is proposed for twolayer VLSI routing. This approach is able to handle any types of routing, and allows arbitrary number of wire segments split at a via candidate.
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